1. Field of the Invention
The present invention relates to a delay insensitive (DI) data transfer apparatus with low power consumption; and, more particularly, to a delay insensitive data transfer apparatus essential to a globally asynchronous locally synchronous (GALS) system.
This work was supported by the IT R&D program for MIC/IITA [2005-S-405-02, “A Development of the Next Generation Internet Server Technology”].
2. Description of Related Art
As a fabrication technology is rapidly developed, devices are highly integrated and a chip size gradually becomes large, so that interconnects become complicated. Therefore, the number and length of transmission lines and delay variability between the transmission lines become the most important factors in design for correct operations of a chip. Under these circumstances, many studies have been conducted to apply a globally asynchronous locally synchronous (GALS) system to a system on chip (SoC) design so as to solve a problem of a typical design to drive an entire chip by using a single clock, considering a delay time of a transmission line.
The GALS system integrates a plurality of modules driven with independent clocks by using an asynchronous handshake protocol and performs a data transfer between the modules. Thus, the GALS system necessarily requires a delay insensitive data transfer scheme that can stably transfer data, regardless of length of a transmission line within a semiconductor chip.
A dual-rail scheme and a 1-of-4 scheme have been proposed as a representative delay insensitive data transfer scheme. However, these schemes require (2N+1) lines for an N-bit data transfer. Due to the increase in the number of the lines, power consumption and/or design complexity may increase. In addition to the delay insensitive data transfer scheme, many studies have been conducted on multi-valued logic circuits for reducing the number of lines necessary for the data transfer. A variety of inventions associated with data transfer schemes using multi-valued logic circuits will be described below.
Korean Patent Registration No. 10-447217, entitled “SIGNAL TRANSMISSION/RECEPTION DEVICE OF NEW WIRING SYSTEM” discloses a signal transmission/reception device of a new wiring system, which can reduce a wiring area by simultaneously transmitting different kinds of signals through one transmission line between plural functional blocks within an integrated circuit. Theoretically, in the case of an N-bit data transfer, voltage values of 2N triangular pulses are encoded and transmitted through one transmission line, and a receiver circuit detects the encoded voltage values and recovers data. In this way, the number of transmission lines required for wiring is reduced and an entire area of an integrated circuit is reduced. However, as the number of the voltage values that can be encoded in the transmission line increases, the number of logics to be decoded increases. Thus, the complexity of the receiver circuit may significantly increase, and the reduction in the number of the transmission lines is limited. As a supply voltage in the integrated circuit is lowered, the multi-valued logic circuit technology using the voltages used in Korean Patent Publication No. 10-447217 may degrade voltage-noise margin characteristic in the receiver circuit.
U.S. Patent Publication No. 2003-0107411, entitled “LOW POWER NRZ INTERCONNECT FOR PULSED SIGNALING”, discloses a current mode multi-valued logic circuit, not a voltage mode. In U.S. Patent Publication No. 2003-0107411, input data signals are transferred through a differential transmission line in a pulse form. A rising edge and a falling edge of a voltage level input signal are sensed and encoded, and then converted into a current level signal. Likewise, the receiver converts the current-level signal into a voltage-level signal and decodes it by using a differential amplifier. In U.S. Patent Publication No. 2003-0107411, a current-level differential transmission line is used for reducing power consumption generated when data is transmitted in a return-to-zero format. However, since 2N transmission lines are required for N-bit data transfer, the proposed data transfer apparatus has no effect in reducing the number of the transmission lines. Further, although the proposed apparatus can be applied to an inter-chip interface on a board, it is not suitable to an inter-module data transfer inside a chip.
The objects of Korean Patent registration No. 10-447217 and U.S. Patent Publication No. 2003-0107411 are to reduce the wiring area by reducing the number of the transmission lines and to reduce the power consumption of the inter-chip interface. However, since the conventional apparatuses do not provide the function for supporting the handshake protocol necessary for the delay insensitive data transfer, they cannot be applied to the GALS system.
Apparatuses using multi-valued logic circuits have been proposed for supporting the delay insensitive data transfer and reducing the number of transmission lines necessary for the delay insensitive data transfer. Korean Patent Registration No. 10-609368 discloses a delay insensitive data transfer apparatus using a current mode multi-valued logic circuit. Due to the use of the current mode multi-valued circuit, the data transfer apparatus is not affected by a noise margin of a supply voltage and three logics per one transmission line are expressed. Thus, (N+1) transmission lines are required for N-bit data transfer. Further, since the data transfer apparatus supports a synchronization circuit, it can be applied to the GALS system. Moreover, compared with the existing delay insensitive data transfer apparatus, the wiring area and the power consumption can be reduced as much as the reduced number of the transmission lines. However, in Korean Patent Registration No. 609368, the weight of static power is great. Therefore, the data transfer apparatus is susceptible in view of power consumption as a transfer rate becomes lower. A lot of power is consumed even in an idle mode in which data are not transferred. This is contrary to contributing to the power consumption by reducing the number of the transmission lines. Rather, this may cause adverse affects in view of power consumption.